1. Field of the Invention
The present invention relates to memory devices based on phase change based memory material, including chalcogenide materials and other programmable resistive materials, and to methods for operating such devices.
2. Description of Related Art
Phase change based memory materials, like chalcogenide materials and similar materials, can be caused to change phase between an amorphous and a crystalline phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous phase is characterized by higher electrical resistivity than the generally crystalline phase, which can be readily sensed to indicate data. These properties have generated interest in using phase change based material to form nonvolatile memory circuits, which can be read and written with random access.
In phase change memory, data is stored by causing transitions in an active region of the phase change material between amorphous and crystalline phases. FIG. 1 is an example distribution of the resistance for a number of memory cells having one of two resistance states (storing a single bit of data). The memory cells each include a phase change memory element which is programmable to a high resistance reset state 102 and a lower resistance set state 100. Each resistance state corresponds to a non-overlapping resistance range. In multi-bit operation the phase change memory elements are programmable to more than two resistance states.
The change from the high resistance state 102 to the lower resistance state 100, referred to as set herein, is generally a lower current operation in which current heats the phase change material above a transition temperature to cause a transition of the active region from the amorphous to the crystalline phase. The change from the lower resistance state 100 to the high resistance state 102, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous phase.
The difference between the highest resistance R1 of the lower resistance state 100 and the lowest resistance R2 of the high resistance state 102 defines a read margin used to distinguish cells in the lower resistance state 100 from those in the high resistance state 102. The data stored in a memory cell can be determined by determining whether the memory cell has a resistance corresponding to the lower resistance state 100 or to the high resistance state 102, for example by sensing whether the resistance of the memory cell is above or below a threshold resistance value RSA 103 within the read margin.
One problem arising in phase change memory devices involves data retention in the high resistance state 102. Specifically, memory cells in the high resistance state 102 can suffer a decrease in resistance, as the active region shifts from amorphous phase to crystalline phase, due to re-crystallization of small portions of the active region. The rate of decrease in resistance depends on a number of factors, including variations in structure and materials across an array, manufacturing defects and environmental conditions to which the device is exposed.
It has been observed that a number of memory cells in an array initially exhibit, or will develop after repeated reset and/or set operations, persistently short retention times in the high resistance state 102, as its resistance quickly decreases over time to below the threshold resistance value RSA 103. As a result, when these memory cells (referred to herein as defect cells) are read the lower resistance state 100 will be detected, resulting in bit errors.
Defect cells can arise due to variations in materials and manufacturing processes which result in different reset characteristics among the memory cells in an array, including differences in the amount of current required to reset the memory cells. For example, variations in structure across an array, such as variations in the shape and size of electrodes and phase change material elements, result in differences in current density within the phase change material elements. As a result, the active regions of the memory cells across the array are subject to different thermal and electrical conditions, resulting in a wide variation in the amount of amorphous phase material in the active regions. This will result in some memory cells (defect cells) in the high resistance state 102 having a comparatively small amount of amorphous phase material in their active regions, for example having a large concentration of crystalline phase material, and/or having a relatively small active region size. As a result, after a relatively short amount of time, a low resistance crystalline phase path can be formed through the active regions of these defect cells, resulting in bit errors. Furthermore, because phase change memory resistance depends upon a number of factors, the memory cells which will experience a rapid decrease in resistance and are thus defect cells may not be identified based on their initial resistance value.
Attempts at addressing the differences in the amount of current required to reset the memory cells include choosing a single, suitably high reset current. However, this results in at least some of the memory cells receiving significantly higher current levels than are necessary to cause a transition to the higher resistance state 102, referred to herein as being “over-reset”. Since the phase change material undergoes a phase change as a result of heating, using unnecessarily high current levels can result in electrical and mechanical reliability problems for the memory cells. These problems include the formation of voids at the phase change material/electrode interfaces due to mechanical stress caused by thermal expansion and material density changes during operation. Additionally, using significantly higher current levels than necessary can result in problems such as localized heating sufficient to induce diffusion/reaction of electrode and phase change material, and/or cause compositional changes in the phase change material within the active region, resulting resistive switching degradation and possible failure of the memory cell.
Defect cells can also arise due to a persistently small retention time in the high resistance state 102 which develops during the life of the device. For example, the amount of amorphous phase material may decrease in response to a given reset operation following repeated set and reset operations, due to compositional changes within the phase change material and diffusion/reaction of electrode material and phase change material.
It is therefore desirable to provide phase change based memory devices and methods for operating which address the data retention issues caused by defect cells.